A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having wirings formed by damascene and its manufacture method.
B) Description of the Related Art
Material having a dielectric constant lower than that of silicon oxide and the like is used as the material of an interlayer insulating film of a wiring layer in order to reduce parasitic capacitance. In order to further lower a dielectric constant, a structure is being adopted which does not use an etching stopper film having a relatively high dielectric constant. When wirings are formed by dual damascene, if an etching stopper is omitted between a via hole layer and a wiring trench layer, it becomes difficult to control the shapes of a wiring trench and a via hole.
As via holes and wiring trenches become finer, it becomes difficult to fill via holes and wiring trenches with conductive material at good reproductivity. JP-A-2003-92349 (FIG. 9) discloses a technique of improving filling characteristics by forming an inclined plane on upper edge portions of sidewalls of a via hole and a wiring trench.
JP-A-2001-284449 discloses a technique of depositing a barrier metal film on sidewalls of a via hole and a wiring trench while a barrier metal layer deposited on the bottom of the via hole is sputtered. This technique improves resistance against electromigration of wirings.
JP-A-2004-165336 discloses a method of covering an inner surface of a via hole with a barrier metal film, etching and removing the barrier metal film on the bottoms and depositing again a barrier metal film on the thinned barrier metal film on the inner surfaces other than the bottoms. This method can thin the barrier metal film on the via hole bottom and retain a sufficient thickness of the barrier metal film on the sidewall of the via hole and on the inner surface of a wiring trench.
In a barrier metal film depositing process, yield and wiring reliability can be improved by adopting sputtering combining depositing and etching. It has been found that during sputter-etching of a barrier metal film, the barrier metal film deposited on an inclined plane having an inclination angle of about 45° relative to a substrate surface is etched faster than the barrier metal film deposited on other surfaces. This may be ascribed to that an etching rate becomes maximum at an incidence angle of about 45° of sputtering ions.
If the inner surfaces of a via hole and a wiring trench have an inclined plane having an inclination angle of 45°, the barrier metal film deposited on this inclined plane is thinned. Voids or the like are formed in the via hole and wiring reliability is lowered. If a barrier metal film is again deposited on the thinned barrier metal film by using the method disclosed in JP-2004-165336, the barrier metal layer in other areas becomes too thick.